Method for producing semiconductor device

ABSTRACT

A method for producing a semiconductor device includes depositing an oxide film containing an impurity having a first conductivity type on a substrate. A nitride film and an oxide film containing an impurity having a second conductivity type different from the first conductivity type are deposited. The oxide film having the first conductivity type, the nitride film, and the oxide film having the second conductivity type are etched to form a contact hole. Epitaxial growth is performed in the contact hole to form a pillar-shaped silicon layer. The nitride film is removed and a metal is deposited to form an output terminal.

RELATED APPLICATIONS

The present application is a divisional application of U.S. applicationSer. No. 14/743,570 filed Jun. 18, 2015, which claims priority toPCT/JP2014/068707, filed Jul. 14, 2014, the entire contents of which areincorporated herein by reference.

BACKGROUND 1. Technical Field

The present invention relates to a method for producing a semiconductordevice and a semiconductor device.

2. Description of the Related Art

The degree of integration of semiconductor integrated circuits, inparticular, integrated circuits using MOS transistors has beenincreasing. With the increasing degree of integration, the size of MOStransistors used in integrated circuits has been decreased to nano-scaledimensions. Such a decrease in the size of MOS transistors causesdifficulty in suppressing leak currents, which poses a problem in thatit is hard to reduce the area occupied by the circuits because of therequirements of the secure retention of necessary currents. To addressthe problem, a surrounding gate transistor (hereinafter referred to asan “SGT”) having a structure in which a source, a gate, and a drain arearranged vertically with respect to a substrate and a gate electrodesurrounds a pillar-shaped semiconductor layer has been proposed (e.g.,refer to Japanese Unexamined Patent Application Publication Nos.2-71556, 2-188966, and 3-145761).

In known inverters that use an SGT, a single transistor is formed in asingle silicon pillar, and an nMOS transistor constituted by a singlesilicon pillar and a pMOS transistor constituted by a single siliconpillar are formed on a plane (e.g., refer to Japanese Unexamined PatentApplication Publication No. 2008-300558). Since at least two siliconpillars are formed on a plane, an area corresponding to the at least twosilicon pillars is required.

In known nonvolatile memories, a plurality of gates are formed in asingle silicon pillar (e.g., refer to Japanese Unexamined PatentApplication Publication No. 2014-57068). A gate insulating film isformed on a sidewall of the silicon pillar, and a source line and a bitline are connected to an upper end and a lower end of the siliconpillar, respectively.

SUMMARY

Accordingly, an object is to provide an inverter circuit formed of asingle semiconductor pillar.

A semiconductor device according to an embodiment of the presentinvention includes a third first-conductivity-type semiconductor layerformed on a semiconductor substrate; a first pillar-shaped semiconductorlayer formed on the semiconductor substrate, the first pillar-shapedsemiconductor layer including a first first-conductivity-typesemiconductor layer, a first body region, a secondfirst-conductivity-type semiconductor layer, a firstsecond-conductivity-type semiconductor layer, a second body region, asecond second-conductivity-type semiconductor layer, and a thirdsecond-conductivity-type semiconductor layer formed from a substrateside in that order; a first gate insulating film formed around the firstbody region; a first gate formed around the first gate insulating film;a second gate insulating film formed around the second body region; asecond gate formed around the second gate insulating film; an outputterminal connected to the second first-conductivity-type semiconductorlayer and the first second-conductivity-type semiconductor layer; and afirst contact that connects the first gate and the second gate.

The first gate insulating film may be further formed on an upper surfaceand a lower surface of the first gate, and the second gate insulatingfilm may be further formed on an upper surface and a lower surface ofthe second gate.

The semiconductor device may include a first connection region formedbetween the second first-conductivity-type semiconductor layer and thefirst second-conductivity-type semiconductor layer.

The semiconductor device may include a first insulating film thatsurrounds the first first-conductivity-type semiconductor layer, asecond insulating film that surrounds the second first-conductivity-typesemiconductor layer, a third insulating film that surrounds the firstsecond-conductivity-type semiconductor layer, and a fourth insulatingfilm that surrounds the second second-conductivity-type semiconductorlayer. The first insulating film contains the same impurity as that ofthe first first-conductivity-type semiconductor layer, the secondinsulating film contains the same impurity as that of the secondfirst-conductivity-type semiconductor layer, the third insulating filmcontains the same impurity as that of the first second-conductivity-typesemiconductor layer, and the fourth insulating film contains the sameimpurity as that of the second second-conductivity-type semiconductorlayer.

A method for producing a semiconductor device according to an embodimentof the present invention includes depositing a second insulating filmthat is an oxide film containing an impurity having a first conductivitytype on a substrate, depositing a sixth insulating film that is anitride film, depositing a third insulating film that is an oxide filmcontaining an impurity having a second conductivity type which is aconductivity type different from the first conductivity type, etchingthe second insulating film, the sixth insulating film, and the thirdinsulating film to form a contact hole, performing epitaxial growth inthe contact hole to form a first pillar-shaped silicon layer; andremoving the sixth insulating film and depositing a metal to form anoutput terminal.

By performing a heat treatment after the step of performing epitaxialgrowth in the contact hole to form a first pillar-shaped silicon layer,a second first-conductivity-type semiconductor layer and a firstsecond-conductivity-type semiconductor layer may be formed in the firstpillar-shaped silicon layer.

According to the present invention, there can be provided an invertercircuit formed of a single semiconductor pillar.

An inverter formed of a single semiconductor pillar is constituted by athird first-conductivity-type semiconductor layer formed on asemiconductor substrate; a first pillar-shaped semiconductor layerformed on the semiconductor substrate, the first pillar-shapedsemiconductor layer including a first first-conductivity-typesemiconductor layer, a first body region, a secondfirst-conductivity-type semiconductor layer, a firstsecond-conductivity-type semiconductor layer, a second body region, asecond second-conductivity-type semiconductor layer, and a thirdsecond-conductivity-type semiconductor layer formed from a substrateside in that order; a first gate insulating film formed around the firstbody region; a first gate formed around the first gate insulating film;a second gate insulating film formed around the second body region; asecond gate formed around the second gate insulating film; an outputterminal connected to the second first-conductivity-type semiconductorlayer and the first second-conductivity-type semiconductor layer; and afirst contact that connects the first gate and the second gate.Therefore, an inverter can be achieved in an area corresponding to asingle semiconductor pillar.

The first gate insulating film is further formed on an upper surface anda lower surface of the first gate, and the second gate insulating filmis further formed on an upper surface and a lower surface of the secondgate. Therefore, insulation of the first gate in a vertical directionand insulation of the second gate in a vertical direction can beachieved with certainty.

The semiconductor device includes a first connection region formedbetween the second first-conductivity-type semiconductor layer and thefirst second-conductivity-type semiconductor layer. Therefore, thesecond first-conductivity-type semiconductor layer and the firstsecond-conductivity-type semiconductor layer can be separated from eachother, and the second first-conductivity-type semiconductor layer thatextends to the connection region and the first second-conductivity-typesemiconductor layer that extends to the connection region can beconnected to the output terminal.

The semiconductor device includes a first insulating film that surroundsthe first first-conductivity-type semiconductor layer, a secondinsulating film that surrounds the second first-conductivity-typesemiconductor layer, a third insulating film that surrounds the firstsecond-conductivity-type semiconductor layer, and a fourth insulatingfilm that surrounds the second second-conductivity-type semiconductorlayer. The first insulating film contains the same impurity as that ofthe first first-conductivity-type semiconductor layer, the secondinsulating film contains the same impurity as that of the secondfirst-conductivity-type semiconductor layer, the third insulating filmcontains the same impurity as that of the first second-conductivity-typesemiconductor layer, and the fourth insulating film contains the sameimpurity as that of the second second-conductivity-type semiconductorlayer. Therefore, semiconductor layers having different conductivitytypes can be formed in a single pillar-shaped semiconductor layerthrough solid-state diffusion.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1A is a plan view illustrating a semiconductor device according toan embodiment of the present invention, FIG. 1B is a sectional viewtaken along line x-x′ of FIG. 1A, and FIG. 1C is a sectional view takenalong line y-y′ of FIG. 1A;

FIG. 2A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 2B is a sectional view taken along line x-x′ of FIG. 2A,and FIG. 2C is a sectional view taken along line y-y′ of FIG. 2A;

FIG. 3A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 3B is a sectional view taken along line x-x′ of FIG. 3A,and FIG. 3C is a sectional view taken along line y-y′ of FIG. 3A;

FIG. 4A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 4B is a sectional view taken along line x-x′ of FIG. 4A,and FIG. 4C is a sectional view taken along line y-y′ of FIG. 4A;

FIG. 5A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 5B is a sectional view taken along line x-x′ of FIG. 5A,and FIG. 5C is a sectional view taken along line y-y′ of FIG. 5A;

FIG. 6A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 6B is a sectional view taken along line x-x′ of FIG. 6A,and FIG. 6C is a sectional view taken along line y-y′ of FIG. 6A;

FIG. 7A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 7B is a sectional view taken along line x-x′ of FIG. 7A,and FIG. 7C is a sectional view taken along line y-y′ of FIG. 7A;

FIG. 8A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 8B is a sectional view taken along line x-x′ of FIG. 8A,and FIG. 8C is a sectional view taken along line y-y′ of FIG. 8A;

FIG. 9A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 9B is a sectional view taken along line x-x′ of FIG. 9A,and FIG. 9C is a sectional view taken along line y-y′ of FIG. 9A;

FIG. 10A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 10B is a sectional view taken along line x-x′ of FIG.10A, and FIG. 10C is a sectional view taken along line y-y′ of FIG. 10A;

FIG. 11A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 11B is a sectional view taken along line x-x′ of FIG.11A, and FIG. 11C is a sectional view taken along line y-y′ of FIG. 11A;

FIG. 12A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 12B is a sectional view taken along line x-x′ of FIG.12A, and FIG. 12C is a sectional view taken along line y-y′ of FIG. 12A;

FIG. 13A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention,

FIG. 13B is a sectional view taken along line x-x′ of FIG. 13A, and FIG.13C is a sectional view taken along line y-y′ of FIG. 13A;

FIG. 14A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 14B is a sectional view taken along line x-x′ of FIG.14A, and FIG. 14C is a sectional view taken along line y-y′ of FIG. 14A;

FIG. 15A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 15B is a sectional view taken along line x-x′ of FIG.15A, and FIG. 15C is a sectional view taken along line y-y′ of FIG. 15A;

FIG. 16A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 16B is a sectional view taken along line x-x′ of FIG.16A, and FIG. 16C is a sectional view taken along line y-y′ of FIG. 16A;

FIG. 17A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 17B is a sectional view taken along line x-x′ of FIG.17A, and FIG. 17C is a sectional view taken along line y-y′ of FIG. 17A;

FIG. 18A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 18B is a sectional view taken along line x-x′ of FIG.18A, and FIG. 18C is a sectional view taken along line y-y′ of FIG. 18A;

FIG. 19A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 19B is a sectional view taken along line x-x′ of FIG.19A, and FIG. 19C is a sectional view taken along line y-y′ of FIG. 19A;

FIG. 20A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 20B is a sectional view taken along line x-x′ of FIG.20A, and FIG. 20C is a sectional view taken along line y-y′ of FIG. 20A;

FIG. 21A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 21B is a sectional view taken along line x-x′ of FIG.21A, and FIG. 21C is a sectional view taken along line y-y′ of FIG. 21A;

FIG. 22A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 22B is a sectional view taken along line x-x′ of FIG.22A, and FIG. 22C is a sectional view taken along line y-y′ of FIG. 22A;

FIG. 23A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 23B is a sectional view taken along line x-x′ of FIG.23A, and FIG. 23C is a sectional view taken along line y-y′ of FIG. 23A;

FIG. 24A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 24B is a sectional view taken along line x-x′ of FIG.24A, and FIG. 24C is a sectional view taken along line y-y′ of FIG. 24A;

FIG. 25A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 25B is a sectional view taken along line x-x′ of FIG.25A, and FIG. 25C is a sectional view taken along line y-y′ of FIG. 25A;

FIG. 26A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 26B is a sectional view taken along line x-x′ of FIG.26A, and FIG. 26C is a sectional view taken along line y-y′ of FIG. 26A;

FIG. 27A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 27B is a sectional view taken along line x-x′ of FIG.27A, and FIG. 27C is a sectional view taken along line y-y′ of FIG. 27A;

FIG. 28A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 28B is a sectional view taken along line x-x′ of FIG.28A, and FIG. 28C is a sectional view taken along line y-y′ of FIG. 28A;

FIG. 29A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 29B is a sectional view taken along line x-x′ of FIG.29A, and FIG. 29C is a sectional view taken along line y-y′ of FIG. 29A;

FIG. 30A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 30B is a sectional view taken along line x-x′ of FIG.30A, and FIG. 30C is a sectional view taken along line y-y′ of FIG. 30A;

FIG. 31A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 31B is a sectional view taken along line x-x′ of FIG.31A, and FIG. 31C is a sectional view taken along line y-y′ of FIG. 31A;

FIG. 32A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 32B is a sectional view taken along line x-x′ of FIG.32A, and FIG. 32C is a sectional view taken along line y-y′ of FIG. 32A;

FIG. 33A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 33B is a sectional view taken along line x-x′ of FIG.33A, and FIG. 33C is a sectional view taken along line y-y′ of FIG. 33A;

FIG. 34A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 34B is a sectional view taken along line x-x′ of FIG.34A, and FIG. 34C is a sectional view taken along line y-y′ of FIG. 34A;

FIG. 35A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 35B is a sectional view taken along line x-x′ of FIG.35A, and FIG. 35C is a sectional view taken along line y-y′ of FIG. 35A;

FIG. 36A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 36B is a sectional view taken along line x-x′ of FIG.36A, and FIG. 36C is a sectional view taken along line y-y′ of FIG. 36A;

FIG. 37A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 37B is a sectional view taken along line x-x′ of FIG.37A, and FIG. 37C is a sectional view taken along line y-y′ of FIG. 37A;

FIG. 38A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 38B is a sectional view taken along line x-x′ of FIG.38A, and FIG. 38C is a sectional view taken along line y-y′ of FIG. 38A;

FIG. 39A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 39B is a sectional view taken along line x-x′ of FIG.39A, and FIG. 39C is a sectional view taken along line y-y′ of FIG. 39A;

FIG. 40A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 40B is a sectional view taken along line x-x′ of FIG.40A, and FIG. 40C is a sectional view taken along line y-y′ of FIG. 40A;

FIG. 41A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 41B is a sectional view taken along line x-x′ of FIG.41A, and FIG. 41C is a sectional view taken along line y-y′ of FIG. 41A;

FIG. 42A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 42B is a sectional view taken along line x-x′ of FIG.42A, and FIG. 42C is a sectional view taken along line y-y′ of FIG. 42A;

FIG. 43A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 43B is a sectional view taken along line x-x′ of FIG.43A, and FIG. 43C is a sectional view taken along line y-y′ of FIG. 43A;

FIG. 44A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 44B is a sectional view taken along line x-x′ of FIG.44A, and FIG. 44C is a sectional view taken along line y-y′ of FIG. 44A;

FIG. 45A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 45B is a sectional view taken along line x-x′ of FIG.45A, and FIG. 45C is a sectional view taken along line y-y′ of FIG. 45A;

FIG. 46A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 46B is a sectional view taken along line x-x′ of FIG.46A, and FIG. 46C is a sectional view taken along line y-y′ of FIG. 46A;

FIG. 47A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 47B is a sectional view taken along line x-x′ of FIG.47A, and FIG. 47C is a sectional view taken along line y-y′ of FIG. 47A;

FIG. 48A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 48B is a sectional view taken along line x-x′ of FIG.48A, and FIG. 48C is a sectional view taken along line y-y′ of FIG. 48A;

FIG. 49A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 49B is a sectional view taken along line x-x′ of FIG.49A, and FIG. 49C is a sectional view taken along line y-y′ of FIG. 49A;

FIG. 50A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 50B is a sectional view taken along line x-x′ of FIG.50A, and FIG. 50C is a sectional view taken along line y-y′ of FIG. 50A;

FIG. 51A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 51B is a sectional view taken along line x-x′ of FIG.51A, and FIG. 51C is a sectional view taken along line y-y′ of FIG. 51A;

FIG. 52A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 52B is a sectional view taken along line x-x′ of FIG.52A, and FIG. 52C is a sectional view taken along line y-y′ of FIG. 52A;

FIG. 53A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 53B is a sectional view taken along line x-x′ of FIG.53A, and FIG. 53C is a sectional view taken along line y-y′ of FIG. 53A;

FIG. 54A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 54B is a sectional view taken along line x-x′ of FIG.54A, and FIG. 54C is a sectional view taken along line y-y′ of FIG. 54A;

FIG. 55A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 55B is a sectional view taken along line x-x′ of FIG.55A, and FIG. 55C is a sectional view taken along line y-y′ of FIG. 55A;

FIG. 56A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 56B is a sectional view taken along line x-x′ of FIG.56A, and FIG. 56C is a sectional view taken along line y-y′ of FIG. 56A;

FIG. 57A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 57B is a sectional view taken along line x-x′ of FIG.57A, and FIG. 57C is a sectional view taken along line y-y′ of FIG. 57A;

FIG. 58A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 58B is a sectional view taken along line x-x′ of FIG.58A, and FIG. 58C is a sectional view taken along line y-y′ of FIG. 58A;

FIG. 59A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 59B is a sectional view taken along line x-x′ of FIG.59A, and FIG. 59C is a sectional view taken along line y-y′ of FIG. 59A;

FIG. 60A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 60B is a sectional view taken along line x-x′ of FIG.60A, and FIG. 60C is a sectional view taken along line y-y′ of FIG. 60A;

FIG. 61A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 61B is a sectional view taken along line x-x′ of FIG.61A, and FIG. 61C is a sectional view taken along line y-y′ of FIG. 61A;

FIG. 62A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 62B is a sectional view taken along line x-x′ of FIG.62A, and FIG. 62C is a sectional view taken along line y-y′ of FIG. 62A;

FIG. 63A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 63B is a sectional view taken along line x-x′ of FIG.63A, and FIG. 63C is a sectional view taken along line y-y′ of FIG. 63A;

FIG. 64A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 64B is a sectional view taken along line x-x′ of FIG.64A, and FIG. 64C is a sectional view taken along line y-y′ of FIG. 64A;

FIG. 65A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 65B is a sectional view taken along line x-x′ of FIG.65A, and FIG. 65C is a sectional view taken along line y-y′ of FIG. 65A;

FIG. 66A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 66B is a sectional view taken along line x-x′ of FIG.66A, and FIG. 66C is a sectional view taken along line y-y′ of FIG. 66A;

FIG. 67A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 67B is a sectional view taken along line x-x′ of FIG.67A, and FIG. 67C is a sectional view taken along line y-y′ of FIG. 67A;

FIG. 68A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 68B is a sectional view taken along line x-x′ of FIG.68A, and FIG. 68C is a sectional view taken along line y-y′ of FIG. 68A;

FIG. 69A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 69B is a sectional view taken along line x-x′ of FIG.69A, and FIG. 69C is a sectional view taken along line y-y′ of FIG. 69A;and

FIG. 70A is a plan view illustrating a method for producing asemiconductor device according to an embodiment of the presentinvention, FIG. 70B is a sectional view taken along line x-x′ of FIG.70A, and FIG. 70C is a sectional view taken along line y-y′ of FIG. 70A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereafter, embodiments of the present invention will be described. FIGS.1A to 1C illustrate a structure of a semiconductor device according toan embodiment of the present invention. In this embodiment, silicon isused as a semiconductor, but a material other than silicon may be usedas a semiconductor.

The semiconductor device includes a third first-conductivity-typesilicon layer 102 formed on a silicon substrate 101 and a firstpillar-shaped silicon layer 116 formed on the silicon substrate 101. Thefirst pillar-shaped silicon layer 116 includes a firstfirst-conductivity-type silicon layer 131, a first body region 202, asecond first-conductivity-type silicon layer 130, a firstsecond-conductivity-type silicon layer 129, a second body region 201, asecond second-conductivity-type silicon layer 128, and a thirdsecond-conductivity-type silicon layer 117 formed from the substrateside in that order. The semiconductor device also includes a first gateinsulating film 125 formed around the first body region 202, a firstgate 126 formed around the first gate insulating film 125, a second gateinsulating film 120 formed around the second body region 201, a secondgate 121 formed around the second gate insulating film 120, an outputterminal 123 connected to the second first-conductivity-type siliconlayer 130 and the first second-conductivity-type silicon layer 129, anda first contact 142 that connects the first gate 126 and the second gate121.

The first gate 126 and the second gate 121 are preferably made of ametal to adjust the threshold of transistors. The metal is preferablytitanium nitride or titanium aluminum nitride. The first gate insulatingfilm 125 and the second gate insulating film 120 are each preferably anoxide film, an oxynitride film, or a high-K dielectric film.

The first gate insulating film 125 is also formed on the upper surfaceand lower surface of the first gate 126. The second gate insulating film120 is also formed on the upper surface and lower surface of the secondgate 121.

The semiconductor device includes a first connection region 203 formedbetween the second first-conductivity-type silicon layer 130 and thefirst second-conductivity-type silicon layer 129.

The semiconductor device also includes a first insulating film 103 thatsurrounds the first first-conductivity-type silicon layer 131 and asecond insulating film 105 that surrounds the secondfirst-conductivity-type silicon layer 130. The first insulating film 103contains the same impurity as that of the first first-conductivity-typesilicon layer 131, and the second insulating film 105 contains the sameimpurity as that of the second first-conductivity-type silicon layer130. The semiconductor device also includes a third insulating film 109that surrounds the first second-conductivity-type silicon layer 129 anda fourth insulating film 111 that surrounds the secondsecond-conductivity-type silicon layer 128. The third insulating film109 contains the same impurity as that of the firstsecond-conductivity-type silicon layer 129, and the fourth insulatingfilm 111 contains the same impurity as that of the secondsecond-conductivity-type silicon layer 128.

When the transistor in a lower portion is an nMOS transistor, the firstinsulating film 103 and the second insulating film 105 are eachpreferably an oxide film containing phosphorus or arsenic in a highconcentration. When the transistor in an upper portion is a pMOStransistor, the third insulating film 109 and the fourth insulating film111 are each preferably an oxide film containing boron in a highconcentration. When the transistor in a lower portion is a pMOStransistor, the first insulating film 103 and the second insulating film105 are each preferably an oxide film containing boron in a highconcentration. When the transistor in an upper portion is an nMOStransistor, the third insulating film 109 and the fourth insulating film111 are each preferably an oxide film containing phosphorus or arsenicin a high concentration.

A production process for forming a structure of an SGT according to anembodiment of the present invention will be described with reference toFIG. 2A to FIG. 70C. In this embodiment, the substrate is made ofsilicon, but may be made of another semiconductor. In the process ofthis embodiment, nMOS is formed in a lower portion of a pillar-shapedsemiconductor layer and pMOS is formed in an upper portion of thepillar-shaped semiconductor layer. However, pMOS may be formed in thelower portion and nMOS may be formed in the upper portion.

As illustrated in FIGS. 2A to 2C, an impurity is introduced into asilicon substrate 101 to form a third first-conductivity-type siliconlayer 102.

As illustrated in FIGS. 3A to 3C, a first insulating film 103 is formed.The first insulating film 103 is preferably an oxide film and morepreferably an oxide film containing phosphorus or arsenic in a highconcentration. Alternatively, after the formation of the firstinsulating film 103, an impurity may be implanted to form an oxide filmcontaining phosphorus or arsenic in a high concentration.

As illustrated in FIGS. 4A to 4C, a fifth insulating film 104 is formed.The fifth insulating film 104 is preferably a nitride film.

As illustrated in FIGS. 5A to 5C, a second insulating film 105 isformed. The second insulating film 105 is preferably an oxide film andmore preferably an oxide film containing phosphorus or arsenic in a highconcentration. Alternatively, after the formation of the secondinsulating film 105, an impurity may be implanted to form an oxide filmcontaining phosphorus or arsenic in a high concentration.

As illustrated in FIGS. 6A to 6C, a sixth insulating film 106 is formed.The sixth insulating film 106 is preferably a nitride film.

As illustrated in FIGS. 7A to 7C, a first resist 107 is formed.

As illustrated in FIGS. 8A to 8C, the sixth insulating film 106 isetched.

As illustrated in FIGS. 9A to 9C, the first resist 107 is removed.

As illustrated in FIGS. 10A to 10C, a seventh insulating film 108 isformed to perform planarization. The seventh insulating film 108 ispreferably an oxide film.

As illustrated in FIGS. 11A to 11C, the seventh insulating film 108 isetched back to expose the sixth insulating film 106.

As illustrated in FIGS. 12A to 12C, a third insulating film 109 isformed. The third insulating film 109 is preferably an oxide film andmore preferably an oxide film containing boron in a high concentration.Alternatively, after the formation of the third insulating film 109, animpurity may be implanted to form an oxide film containing boron in ahigh concentration.

As illustrated in FIGS. 13A to 13C, an eighth insulating film 110 isformed. The eighth insulating film 110 is preferably a nitride film.

As illustrated in FIGS. 14A to 14C, a fourth insulating film 111 isformed. The fourth insulating film 111 is preferably an oxide film andmore preferably an oxide film containing boron in a high concentration.Alternatively, after the formation of the fourth insulating film 111, animpurity may be implanted to form an oxide film containing boron in ahigh concentration.

As illustrated in FIGS. 15A to 15C, a second resist 112 is formed.

As illustrated in FIGS. 16A to 16C, the fourth insulating film 111, theeighth insulating film 110, the third insulating film 109, the seventhinsulating film 108, the sixth insulating film 106, the secondinsulating film 105, the fifth insulating film 104, and the firstinsulating film 103 are etched.

As illustrated in FIGS. 17A to 17C, the second resist 112 is stripped.

As illustrated in FIGS. 18A to 18C, a ninth insulating film 113 isdeposited to perform planarization. The ninth insulating film 113 ispreferably an oxide film. The presence of the ninth insulating film 113can prevent a pillar-shaped semiconductor layer from bending or topplingwhen the eighth insulating film 110, the sixth insulating film 106, andthe fifth insulating film 104 are removed later.

As illustrated in FIGS. 19A to 19C, a third resist 114 is formed.

As illustrated in FIGS. 20A to 20C, the ninth insulating film 113, thefourth insulating film 111, the eighth insulating film 110, the thirdinsulating film 109, the sixth insulating film 106, the secondinsulating film 105, the fifth insulating film 104, and the firstinsulating film 103 are etched to form a contact hole 115.

As illustrated in FIGS. 21A to 21C, the third resist 114 is removed.

As illustrated in FIGS. 22A to 22C, a first pillar-shaped silicon layer116 is formed by performing epitaxial growth. A polysilicon may bedeposited.

As illustrated in FIGS. 23A to 23C, boron is introduced as an impurityto form a third second-conductivity-type silicon layer 117.

As illustrated in FIGS. 24A to 24C, a polysilicon 118 is deposited. Apolysilicon is used herein, but any material that serves as a hard maskmay be used.

As illustrated in FIGS. 25A to 25C, a fourth resist 119 is formed.

As illustrated in FIGS. 26A to 26C, the polysilicon 118, the ninthinsulating film 113, and the fourth insulating film 111 are etched.

As illustrated in FIGS. 27A to 27C, the fourth resist 119 is removed.

As illustrated in FIGS. 28A to 28C, the eighth insulating film 110 isetched. Wet etching is preferably employed.

As illustrated in FIGS. 29A to 29C, a second gate insulating film 120 isformed. The second gate insulating film 120 is preferably an oxide film,an oxynitride film, or a high-K dielectric film.

As illustrated in FIGS. 30A to 30C, a metal 121 to be a second gate 121is formed. The metal 121 is preferably titanium nitride or titaniumaluminum nitride.

As illustrated in FIGS. 31A to 31C, the metal 121 is etched to form asecond gate 121.

As illustrated in FIGS. 32A to 32C, the exposed second gate insulatingfilm 120 and the third insulating film 109 are etched to expose thesixth insulating film 106.

As illustrated in FIGS. 33A to 33C, a tenth insulating film 122 isdeposited. The tenth insulating film 122 is preferably an oxide film.

As illustrated in FIGS. 34A to 34C, the tenth insulating film 122 isetched so as to be left as a sidewall.

As illustrated in FIGS. 35A to 35C, the sixth insulating film 106 isetched. Wet etching is preferably employed.

As illustrated in FIGS. 36A to 36C, a metal 123 to be an output terminal123 is formed. The metal 123 is preferably titanium nitride, titaniumaluminum nitride, or tungsten.

As illustrated in FIGS. 37A to 37C, the metal 123 is etched to form anoutput terminal 123.

As illustrated in FIGS. 38A to 38C, the second insulating film 105 isetched to expose the fifth insulating film 104.

As illustrated in FIGS. 39A to 39C, an eleventh insulating film 124 isdeposited. The eleventh insulating film 124 is preferably an oxide film.

As illustrated in FIGS. 40A to 40C, the eleventh insulating film 124 isetched so as to be left as a sidewall.

As illustrated in FIGS. 41A to 41C, the fifth insulating film 104 isetched. Wet etching is preferably employed.

As illustrated in FIGS. 42A to 42C, a first gate insulating film 125 isformed. The first gate insulating film 125 is preferably an oxide film,an oxynitride film, or a high-K dielectric film.

As illustrated in FIGS. 43A to 43C, a metal 126 to be a first gate 126is formed. The metal 126 is preferably titanium nitride or titaniumaluminum nitride.

As illustrated in FIGS. 44A to 44C, the metal 126 is etched to form afirst gate 126.

As illustrated in FIGS. 45A to 45C, the exposed first gate insulatingfilm 125 is etched.

As illustrated in FIGS. 46A to 46C, a first interlayer insulating film127 is deposited to perform planarization. Thus, the polysilicon 118 isexposed.

As illustrated in FIGS. 47A to 47C, the polysilicon 118 is etched.Herein, part of the third second-conductivity-type silicon layer 117 isetched.

As illustrated in FIGS. 48A to 48C, a heat treatment is performed toform a first first-conductivity-type silicon layer 131, a secondfirst-conductivity-type silicon layer 130, a firstsecond-conductivity-type silicon layer 129, and a secondsecond-conductivity-type silicon layer 128 through solid-statediffusion. The heat treatment may be performed before the formation ofthe second gate 121.

As illustrated in FIGS. 49A to 49C, a fifth resist 132 is formed.

As illustrated in FIGS. 50A to 50C, the ninth insulating film 113 andthe second gate insulating film 120 are etched.

As illustrated in FIGS. 51A to 51C, the second gate 121 is etched.

As illustrated in FIGS. 52A to 52C, the second gate insulating film 120is etched.

As illustrated in FIGS. 53A to 53C, the fifth resist 132 is removed.

As illustrated in FIGS. 54A to 54C, a second interlayer insulating film133 is deposited to perform planarization.

As illustrated in FIGS. 55A to 55C, the second interlayer insulatingfilm 133 is etched back to expose the third second-conductivity-typesilicon layer 117.

As illustrated in FIGS. 56A to 56C, a sixth resist 134 is formed.

As illustrated in FIGS. 57A to 57C, the first interlayer insulating film127 is etched to form a contact hole 135.

As illustrated in FIGS. 58A to 58C, the sixth resist 134 is removed.

As illustrated in FIGS. 59A to 59C, a seventh resist 136 is formed.

As illustrated in FIGS. 60A to 60C, the second interlayer insulatingfilm 133 is etched to form a contact hole 137.

As illustrated in FIGS. 61A to 61C, the seventh resist 136 is removed.

As illustrated in FIGS. 62A to 62C, an eighth resist 138 is formed.

As illustrated in FIGS. 63A to 63C, the ninth insulating film 113 andthe second gate insulating film 120 are etched.

As illustrated in FIGS. 64A to 64C, the second gate 121 is etched.

As illustrated in FIGS. 65A to 65C, the second gate insulating film 120,the third insulating film 109, the seventh insulating film 108, thesecond insulating film 105, and the first gate insulating film 125 areetched to form a contact hole 139.

As illustrated in FIGS. 66A to 66C, the eighth resist 138 is removed.

As illustrated in FIGS. 67A to 67C, a metal 143 is deposited to formcontacts 140 and 141 and a first contact 142.

As illustrated in FIGS. 68A to 68C, ninth resists 144, 145, 146, and 147are formed.

As illustrated in FIGS. 69A to 69C, the metal 143 is etched to formmetal wirings 143 a, 143 b, 143 c, and 143 d.

As illustrated in FIGS. 70A to 70C, the ninth resists 144, 145, 146, and147 are removed.

The method for producing a semiconductor device according to anembodiment of the present invention has been described above.

In the present invention, various embodiments and modifications can bemade without departing from the broad sprit and scope of the presentinvention. Furthermore, the above-described embodiment is provided todescribe one embodiment of the present invention, and the scope of thepresent invention is not limited thereto.

For example, a method for producing a semiconductor device in which thep-type (including the p⁺-type) and the n-type (including the n⁻-type)are each changed to the opposite conductivity type in the aboveembodiment, and a semiconductor device produced by the method are alsoobviously included in the technical scope of the present invention.

1. A method for producing a semiconductor device comprising: depositingan oxide film containing an impurity having a first conductivity type ona substrate; depositing a nitride film; depositing an oxide filmcontaining an impurity having a second conductivity type different fromthe first conductivity type; etching the oxide film having the firstconductivity type, the nitride film, and the oxide film having thesecond conductivity type to form a contact hole; performing epitaxialgrowth in the contact hole to form a pillar-shaped silicon layer;removing the nitride film; and depositing a metal to form an outputterminal.
 2. The method for producing a semiconductor device accordingto claim 1, further comprising: performing a heat treatment after theperforming epitaxial growth in the contact hole to form a firstpillar-shaped silicon layer; and forming a first-conductivity-typesemiconductor layer and a second-conductivity-type semiconductor layerin the pillar-shaped silicon layer.